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Department of Computer Science

Sohn, Andrew

Contact Info
Title: Associate Professor
Email: andrew.sohn@njit.edu
Office: 4209 GITC
Hours: Mon 2:30-4 pm, Thur 4-5:30 pm
Phone: 973-596-2315
Dept: Computer Science
Webpage: http://cs.njit.edu/~sohna

About Me



Education

  • Ph.D. in Computer Engineering, University of Southern California
  • M.S. in Computer Engineering, University of Southern California
  • B.S. in Electrical Engineering, University of Southern California

Courses I Teach

Not teaching any courses this semester

Teaching


Publications

  1. S-J Lee, M. Jeon, D. Kim, A. Sohn, Partitioned Parallel Radix Sort, Journal of Parallel and Distributed Computing 62, September 2002, pp.656-668.
  2. A. Sohn, Y. Kodama, J. Ku, M. Sato, Y. Yamaguchi, Tolerating communication latency through dynamic thread invocation in a multithreaded architecture, (Eds.) S. Pande and D. Argawal, Compiler Optimization for Scalable Parallel Systems, Springer 2001, pp.525-549.
  3. A. Sohn, Y. Paek, J. Ku, Y. Kodama, Y. Yamaguchi, Communication Studies of Three Distributed-Memory Multiprocessors, in Proc. of IEEE Symposium on High Performance Computer Architecture, Orlando, Florida, January 1999, pp.310-314. (Technical Report, NJIT CIS-98-3, May 1998.)
  4. A. Sohn and H. D. Simon, S-HARP: A Scalable Parallel Dynamic Partitioner for Adaptive Computations, in Proc. of Supercomputing 98, November 1998, Orlando, Florida. Presentation slides.
  5. A. Sohn and Y. Kodama, Load Balanced Parallel Radix Sort, in Proc. of the 12th ACM International Conference on Supercomputing, Melbourne, Australia, July 1998, pp.305-312. Presentation slides.
  6. A. Sohn, R. Biswas, Sepcial Issue on Dynamic Load Balancing, Journal of Parallel and Distributed Computing 47, December 1997, pp.99-101.
  7. A. Sohn, Y. Kodama, J. Ku, M. Sato, H. Sakane, H. Yamana, S. Sakai, Y. Yamaguchi, Fine-Grain Multithreading with the EM-X Multiprocessor, in the Ninth ACM Symposium on Parallel Algorithms and Architectures, Newport, Rhode Island, June 1997, pp.189-198. The full version of this paper will be installed in the future.
  8. H. D. Simon, A. Sohn, and R. Biswas, HARP: A Dynamic Spectral Partitioner, Journal of Parallel and Distributed Computing 50, April 1998, pp.88-103. (Also appeared in the Ninth ACM Symposium on Parallel Algorithms and Architectures, Newport, Rhode Island, June 1997, pp.43-52.) Four meshes prepared in color: Spiral and Barth5 in 8 partitions -- Hsctl and Mach95 in 8 partitions. The full version of this paper will be installed in the future.
  9. A. Sohn, M. Sato, N. Yoo, and J-L Gaudiot, Data and Workload Distribution in a Multithreaded Architecture, Journal of Parallel and Distributed Computing 40, February 1997, pp.256-264
  10. A. Sohn, R. Biswas, and H. Simon, Impact of Load Balancing on Unstructured Adaptive Computations for Distributed-Memory Multiprocessors, in Proc. the Eighth IEEE Symposium on Parallel and Distributed Processing, New Orleans, Louisiana, October 1996, pp.26-33.
  11. A. Sohn, J. Ku, Y. Kodama, M. Sato, H. Sakane, H. Yamana, S. Sakai, and Y. Yamaguchi, Identifying the Capability of Overlapping Computation with Communication, in Proc. ACM/IEEE Conference on Parallel Architectures and Compilation Techniques, Boston, MA, October 1996, pp. 133-138.
  12. A. Sohn, Parallel Satisfiability Test with Synchronous Simulated Annealing, Journal of Parallel and Distributed Computing, August 1996, pp.195-204.
  13. A. Sohn, R. Biswas, and H. Simon, A Dynamic Load Balancing Framework for Unstructured Adaptive Computations on Distributed-Memory Multiprocessors, in Proceedings of the 8th ACM Symposium on Parallel Algorithms and Architectures, Padua, Italy, June 1996.
  14. A. Sohn, Parallel N-ary Speculative Computation of Simulated Annealing, IEEE Tranasctions on Parallel and Distributed Systems 6, October 1995, pp.997-1005.
  15. A. Sohn and H. Simon, JOVE: A dynamic load balancing framework for adaptive computations on an SP-2 distributed-memory multiprocessor, NJIT CIS Tech Report 94-40, September 1994.